- Generate and analyze different simultaneous patterns on OC-192/STM-64
For OC-192/STM-64:Any combinations of STS-192c/STS-48c/STS-12c/STS-3c/STS-1c
or any combinations of STM-64c/STM-16c/STM-4c/STM-1c.
For OC-48/STM-16: Any combinations of STS-48c/STS-12c/STS-3c/STS-1c
or any combinations of STM-16c/STM-4c/STM-1c.
- Full overhead access and analysis including detection of change
in overhead bytes by a Receiver Card.
- Error insertion of B1, B2, B3, pattern and random by the Transmitter
- Error detection of B1, B2, B3, pattern and framing by the Receiver
- Internal reference oscillator, external DS-1, or E1 or any receiver
slot for reference timing.
- THRU Mode for distributing a STS-48/STM-16 received signal.
- Control and readout of Path and Transport Overhead.
- DCC drop and insert for line and section.
- Software stored on the CPU/Clock card in flash permitting easy
upgrading of a test system.
- Ethernet 10BaseT interface for control.
- Java graphical interface for full test and control.
- Up to fourteen simultaneous users supported per chassis
- Full range of BER testing
of all concatenated and tributary signals.
- High density testing
for low cost per port.
- Testing for North American
and ITU protocols.
- Highest throughput
for carrier and manufacturing applications.
- JAVA GUI supports multiple
Inc. reserves the right to update the product specifications without
Copyright © 2004